Low Complexity Multiplier for GF ( 2 ) Based All One Polynomialm

The area-time-efficient systolic structure for multiplication over GF (2m) based on irreducible all-one polynomial (AOP) and used a novel cut-set retiming to reduce the duration of the critical-path to one XOR gate delay. Basically, this paper is depends on digital electronics(ie.,logic gates)how to reduce the gate count.Finally it is used for what are techniques available in electronics(VLSI advanced technology).Here going to do is to reduce the power consumption,reduce the gate count,and to reduce the critical path in XOR gate in real time application.In input using the technique called register sharing an cut set retiming in that how to reduce the components and to get in area time efficient of systolic structure. The result obtained is in real time application of security purposes for example ATM,etc., to get the area time efficient systolic structure and security purposes in advanced VLSI technology. The application of the paper is mainly for security purposes and for irreducible polynomial of efficient implementation.